b'Engineer Innovation | ElectronicsValidation of Packaging Thermal ResistanceBrian Philofsky, Principal Technical Marketing Engineer, Xilinx, Inc.Introduction this measurement wrong can lead toof the BGA mounted on a JEDEC 2S2P Perhaps the most useful metric for aover-design and higher costsPCB, in the fixture (shown in Figure 2). thermal engineer when it comes to aassociated with the thermal solutions.Thermal grease is applied between the flip-chip BGA (Ball Grid Array) is theIn order to provide consistentlypackage case and the cold plate and a junction-to-case thermal resistancerepeatable measurement data Xilinxclamping force is applied. The BGA (R ). A lower Rhas direct implicationsbases the Rmeasurement on thepackage is electricaly connected to the JC JC JCon the thermal design required toJEDEC JESD51-14 standard [1]. ThisSimcenter T3STER measurement maintain the temperature of themethod uses the difference inhardware. A heating current is applied device, along with the heat dissipationtransient thermal response for twothrough the electrical connection until and surrounding environment. Athermal interfaces between the casesteady state is reached. At this point package with a lower junction-to-caseand cold plate surfaces to identify thethe heating current is reduced to a thermal resistance has better thermalthermal resistance between thevery low sensing current and the data performance. junction-to-case thermaljunction and case.collection phase of the measurement resistance is one of the metrics thatbegins. The measurement ends when Xilinx publishes in datasheets, asRecently a customer requestedthe lower temperature steady state shown Table 1, to allow designers tocharacterization data of thecondition is reached. The compare thermal performance ofXCZU15EG-FFVB1156 device to validatemeasurement is repeated with a devices. While a low Ris desired, it isthe published JEDEC Rvalue of 0.19different amount of thermal grease JC JCequally important that theK/W. To facilitate this request Xilinxbetween the device and cold plate. measurement result be reproduciblecontracted Mentor, A Siemens on the same device and reliably yieldBusiness to perform an externalThe measurement results are the same value when measuring avalidation of the packaging thermalprocessed in the Simcenter T3STER sample of parts.resistance. Four devices from threeMaster software to produce Structure sources (Customer Production,Functions. The Structure Function Historically junction-to-case thermalCustomer Engineering Sample, andrepresents the Thermal Capacitance measurements involved using aXilinx Production) were provided forvs. Thermal Resistance along the heat thermocouple mounted on the casethe measurement. One of the devicestransfer path from the device junction surface to determine the casemounted on a JEDEC 2S2P PCB isto the cold plate. The structures temperature. For a variety of reasonsshown in Figure 1.derived from each of the two tests will the use of a thermocouple hasntbe identical up to the point they provided the adequate repeatabilityMeasurement Setup separate due to differing amounts of necessary when measuring junction- Each measurement consists of placingthermal grease at the case surface. to-case thermal resistance. Gettingthe device under test, which consistsJEDEC JESD51-14 provides a consistent Package JBJCJC JA-Effective(C/W)Package Body Size Devices (C/W) (C/W) (C/W)@250 LFM @500 LFM @750 LFMXCZU6 1.95 0.17 7.8 5.1 4.2 4.0FFVB1156 35 x35 XCZU9 1.95 0.17 7.8 5.1 4.2 4.0XCZU15 1.82 0.19 7.7 5.0 4.2 4.0Figure 1: Xilinx Package mounted on JEDECTable 1: Thermal Resistance Data2S2P PCB24'